1. Field of the Invention
The present invention generally relates to voltage supplies for integrated circuits, and more particularly to distributed charge pump systems used to power electronic memory structures such as dynamic random-access memory (DRAM).
2. Description of the Related Art
Power management has become a dominant concern in the development of data processing systems. Excess power usage is not only costly and inefficient, but also leads to heat management problems. These problems are particularly pronounced in computer systems having large amounts of memory. State of the art computer systems typically use dynamic random-access memory (DRAM) which is preferable over other memory structures such as static random-access memory (SRAM) because DRAM is more dense. However, DRAM can be more power intensive in circuit blocks for active power supply generation and refresh. SRAM uses a flip-flop memory cell but DRAM uses a capacitor-based memory cell which, due to current leakage, must be regularly refreshed. DRAM can consume a significant portion of a system's overall power.
Power management has become even more challenging with the advent of new memory technologies like embedded DRAM (eDRAM). This new design relies on the silicon-on-insulator (SOI) technology pioneered by International Business Machines Corp. using deep-trench capacitors. Deep-trench (3-dimensional) capacitors have a reduced footprint on the semiconductor substrate, and an eDRAM array has about one-third the area of a comparable DRAM array. Reducing the size of the memory makes it easier to embed the array on the same integrated circuit chip, e.g., a microprocessor or an application-specific integrated circuit (ASIC), to provide a system-on-a-chip solution. An exemplary commercial microprocessor might devote up to 60% of its surface area to memory. Replacing conventional DRAM with eDRAM cells allows the chip designer to build smaller chips and reduce the length of wire that data must travel as it commutes around the chip, resulting in the fastest memory access times ever recorded. Embedding memory further permits much wider buses and higher operation speeds and, due to the much higher density of eDRAM, larger amounts of memory can potentially be used.
An eDRAM array requires an on-chip power supply having precise high and low voltages (positive and negative) for the word lines that drive the rows of the memory array. The high voltage is used to activate a word line, and the low voltage is for standby. FIG. 1 depicts a conventional power supply for an eDRAM array. Power supply 10 includes a reference generator 12, two regulators 14a, 14b, two pump cores 16a, 16b, and a clock source 18. Clock source 18 (phase-locked loop) provides a single clock signal to each of the pump cores 16a, 16b, for example in the range of 20-300 MHz. Pump core 16a provides a high voltage level Vpp to an active voltage rail 20, while pump core 16b provides a low voltage level Vwl to a standby voltage rail 22. The high voltage level Vpp may be referred to a positive voltage and the low voltage level Vwl may be referred to as a negative voltage, but these terms are relative and those skilled in the art will appreciate that both the high and low voltage levels may be positive voltage values. Vpp may be in the range of 1.4 to 1.8 volts and Vwl may be in the range of −0.3 to −0.7 volts.
Rails 20, 22 have pairs of taps connected to respective word line drivers 24-1, 24-n. Each word line driver 24 is used to activate a corresponding row of memory cells in eDRAM array 26. In this example eDRAM array 26 is 1200 cells wide, i.e., each word line is connected to 1200 cells in that row. A memory address for a requested memory block is decoded by memory control logic (not shown) and the resulting signal is used to activate the appropriate word line driver which then switches the voltage for that word line to Vpp while the other word lines are maintained at Vwl. The switching circuitry within a word line driver 24 uses a separate supply voltage Vdd (e.g., around 1.0 volt). Sense lines 28a, 28b connected to the inputs of word line drivers 24 are used to provide feedback to regulators 14a, 14b. Regulators 14a, 14b determine an upper limit of the pump voltages and temporarily disable a pump core if the output voltage exceeds the limit. Reference generator 12 generates an internal stable voltage that is used by regulators 14a, 14b for comparison purposes. Reference generator may be a band gap circuit or voltage divider, or an external reference can be provided.
Various pump designs can be used to deliver the voltages from pump cores 16a, 16b, including for example the Cockcroft-Walton voltage multiplier, the Dickson charge pump, and the Nakagome voltage doubler. The Cockcroft-Walton voltage multiplier uses a ladder network of capacitors and diodes or switches connected to a low voltage input. As a charge cascades through the capacitors it successively increases to finally yield a higher voltage at the output. The Dickson charge pump operates in a similar manner but in the Dickson design the nodes of the diode chain are coupled to the inputs via capacitors in parallel instead of in series. The Nakagome voltage doubler uses switched capacitors whose output nodes are connected to cross-coupled transistors.
Peak electrical current in these charge pumps occurs at the clock signal edges, i.e., rising and falling. While peak current is not particularly troublesome for a single charge pump, it can become excessive in larger systems having multiple charge pumps. For example, a microprocessor chip may include an on-board level 3 (L3) cache memory having 32 megabytes of memory employing 96 charge pumps. If these pumps all run on the same clock signal, charge pump peak power and transient current supply current is multiplied by a factor of 96, which would significantly burden the system power budget and heat sink cost.
Methods have been devised which address peak power consumption in voltage supplies for integrated circuits, but these methods still have various disadvantages. In the construction of application-specific integrated circuits (ASICs), a granular DRAM cell is provided with its own pump and oscillator in a single circuit block. This approach does not work well in high performance systems with large embedded DRAM since instantaneous switching power can still be many times higher. Half-cycle clock edge usage does not affect peak current in switched-capacitor (cross-coupled) charge pumps since both clock phases are already used. In a more recent clock distribution system design (Montecito), a phase-locked loop (PLL) circuit feeds many digital frequency dividers (DFDs) several of which are phase and frequency aligned. Each DFD contains a delay locked loop (DLL) and a state machine that dynamically select among 64 DLL phases. At the second level clock buffer (SLCB) level, regional active deskew phase comparators are used to reduce skews due to process, voltage and temperate variations. Half-rate 0° and 90° differential clocks are multiplied to return to the full rate clock at the SLCB level. This multiplicity of blocks is inefficient for large on-board designs, and also presents problems with variability and the power burden on the clock network itself. In another clock distribution system used for polysilicon thin-film transistor displays, delay elements are employed to achieve phase offsets. This approach requires a time constant match between pump operation and the delay circuit blocks. The delay block is part of the clock excitation path and contributes to pump system power usage. Phase offset by delay stages does not work well for newer technologies (with FO4 delays in the neighborhood of 10 picoseconds) since it may take up to 250 such delay stages to move just one clock edge of a 100 MHz clock by 25% of its period.
On-die regulated voltage level generation is becoming essential to reduce system cost and power delivery complexity in large chips with multiple power islands. In particular, supply generation for eDRAM word lines in server class applications entails special challenges because of the stringent power, performance, cell retention, variability, and distribution requirements. It would, therefore, be desirable to devise an improved charge pump system which can overcome the foregoing problems but still have an efficient energy conversion topology. It would be further advantageous if the system could easily be optimized for active and leakage power.